The present invention relates to an active matrix display device having a plurality of pixels, each having a switching element, and more particularly, to a drive circuit of a display device that is arranged near a display area.
Display devices may be divided into passive matrix display devices and active matrix display devices. An active matrix display device has a plurality of pixels, each of which includes a switching element. The switching element applies a voltage (or supplies a current), which corresponds to image data, to the associated pixel to form an image.
In a liquid crystal display (LCD) device, liquid crystal is sandwiched between opposing substrates. A voltage is applied to pixel electrodes, which are associated with the pixels, to alter the transmittance of the liquid crystal and form an image. An active matrix LCD device is used as a monitor.
In an electroluminescence (EL) display device, current is flowed from pixel electrodes, which are associated with the pixels, to corresponding EL elements to form an image. Research is presently being carried out to put an active matrix EL display device to practical use.
A thin film transistor (TFT) is used as the switching element. To fabricate a TFT semiconductor layer without having to perform a high-temperature process, a so-called low-temperature polysilicon TFT has been proposed. In this case, the TFT is formed after the formation of various types of peripheral circuits on a glass substrate. This decreases the number of drive ICs connected around the display panel and decreases manufacturing costs. The low polysilicon TFT may be employed in active matrix display devices other than the LCD device and the EL display device, such as a plasma display and a field effect display (FED).
FIG. 1 is a schematic block diagram of a prior art active matrix LCD device 500. The LCD device 500 is formed on a glass substrate and includes an LCD panel 100, which has various peripheral circuits, and an external control circuit 200, which is connected to the LCD panel 100.
The external control circuit 200 provides the LCD panel 100 with control signals, image signals, and a power supply voltage VDD to operate the LCD panel 100. The external control circuit 200 is a CMOS circuit and is operated by a low voltage, such as 3V, and generates control signals having amplitudes of 3V.
The LCD panel 100 includes a display area 10 and various peripheral circuits. The display area 10 includes an arrangement of rows and columns of pixel electrodes 11, drain lines 12 extending along the columns of the pixel electrodes 11, and gate lines 13 extending along the rows of the pixel electrodes 11. A selection transistor 14 is arranged at each intersection between the drain lines 12 and the gate lines 13. The drain of each selection transistor 14 is connected to the corresponding drain line 12, the gate is connected to the corresponding gate line 13, and the source is connected to the corresponding pixel electrode 11. A color filter of one of RGB is arranged in each pixel electrode 11 to form a color.
A drain line driver 21, which is connected to the drain lines 12, and a gate line driver 22, which is connected to the gate lines 13, are arranged near the display area 10. A potential conversion circuit 30 is connected between the external control circuit 200, the drain line driver 21, and the gate line driver 22.
The operation of the active matrix display device 500 will now be described. The gate line driver 22 sequentially selects a predetermined gate line 13 from the plurality of gate lines 13 and applies a gate voltage VG to the selected gate line. This activates the selection transistors 14 connected to the selected gate line 13. In response to a vertical start signal (vertical scan signal) VST, the gate line driver 22 selects the first gate line 13 and sequentially switches the selected gate line 13 based on the vertical clock signal VCK.
The drain line driver 21 sequentially selects a predetermined drain line 12 from the plurality of drain lines 12 to provide RGB image signals to the pixel electrode 11 via the selected drain line 12 and the selection transistors 14. The drain line driver 21 simultaneously selects one or more of the drain lines 12. In response to a horizontal start signal (horizontal scan signal) HST, the drain line driver 21 selects the first drain line 12 and sequentially switches the drain line 12 that is to be selected based on a horizontal clock signal HCK.
The potential conversion circuit 30 receives low-voltage clock signals VCKL, HCKL having amplitudes of 3V, from the external control circuit 200 and boosts the low-voltage clock signals VCKL, HCKL, for example, to 12V. This generates the vertical clock signal VCK and the horizontal clock signal HCK. Many pixel electrodes 11 are connected to each drain line 12 and each gate line 13. Thus, the LCD panel 100 cannot be operated by a low voltage of about 3V. Accordingly, the voltage of the control signals provided from the external control circuit 200 is boosted to a high voltage of 12V. The voltage boosting is necessary to reach a predetermined operating speed of the display device 500 with TFTs. The potential conversion circuit 30 includes voltage boosting level shifters 31 and a buffer 32, which increases the current driving capability. The level shifters 31 and the buffer 32 are associated with the control signals.
FIG. 2 is a schematic circuit diagram of the drain line driver 21. The drain line driver 21 includes a scanner 23 and a plurality of RGB selection circuits 24. The scanner 23 includes a plurality of series-connected shift registers 25. Each shift register 25 is provided with the horizontal clock signal HCK, the voltage of which has been boosted by the potential conversion circuit 30. Each RGB selection circuit 24 includes three drain line selection transistors 26, each of which has a gate connected to the output terminal of an associated one of the shift registers 25. The drain of each drain line selection transistor 26 is connected to one of data lines 33R, 33G, 33B. The source of each drain line selection transistor 26 is connected to an associated one of the drain lines 12.
The shift register 25a in the first stage is provided with the horizontal start signal HST. In response to the horizontal start signal HST, the shift register 25a outputs from its output terminal Q a signal having a high level for a period of one cycle of the horizontal clock signal HCK. The output signal of the shift register 25a activates the drain selection transistors 26Ra, 26Ga, 26Ba, and provides image signals from the data lines 33R, 33G, 33B to the drain lines 12Ra, 12Ga, 12Ba, respectively.
The output signal of the shift register 25a is also provided to the shift register 25b in the second stage. The shift register 25b outputs a signal having a high level for a period of next cycle of the horizontal clock signal HCK. The output signal of the shift register 25b activates the drain selection transistors 26Rb, 26Gb, 26Bb and provides image signals from the data lines 33R, 33G, 33B to the drain lines 12Rb, 12Gb, 12Bb, respectively. The output signal of the shift register 25b activates the next shift register 25c and sequentially selects the associated drain lines 12 in the same manner. By operating every shift register in the same manner, every pixel is provided with the image signals.
After the selection of every drain line 12 in one row is completed, the gate line driver 22 provides the next gate line 13 with the gate voltage VG during the next cycle of the vertical clock signal VCK. Then, the horizontal start signal HST is provided to the drain line driver 21 to generate an output signal having a high level from the shift register 25a. Like the drain line driver 21, the gate line driver 22 is a scanner including shift registers.
Since cellular phones and portable information terminals have become popular nowadays, it is required that the power consumed by display devices be low. However, the horizontal clock signal HCK is provided to every shift register 25 of the drain line driver 21. Further, the vertical clock signal VCK is provided to every shift register of the gate line driver 22. A large current driving capability is required to provide the horizontal and vertical clock signals in this manner. This inevitably increases power consumption. The amount of power consumed by the buffer 32 to obtain the required current driving capability is especially large.